Spin Torque Transfer (STT) Magnetoresistive Random Access Memory (MRAM) is an attractive emerging memory technology, offering non-volatility, high performance, and high endurance. An STT MRAM memory cell generally includes a Magnetic Tunnel Junction (MTJ) in series with a Field Effect Transistor (FET) which is gated by a Word Line (WL). A Bit Line (BL) is connected to the MTJ and runs perpendicular to the WL. A Source Line (SL) is connected to the FET.
The SL can be wired within the array in a number of different configurations. One approach is to wire the SL parallel to and at the same pitch as the BL. Another approach is to connect the SL terminals of all cells within a group of BLs together, in what is known as a Common Source Line (CSL) configuration. The grouped BLs often correspond to the domain of a Write Driver circuit. This means that only one cell may be written at a time within that domain.
Advantageously, a CSL configuration can result in a smaller cell and lower SL resistance. However, the CSL configuration places limitations on the methods used to write the cell, as all cells within that region share the same SL.
Thus, improved CSL array biasing schemes would be desirable.